The present invention relates to a semiconductor storage device.
In SRAM (Static Random Access Memory), which is one of semiconductor storage devices, various proposals are made for reduction of a leakage current.
For example, a technique that reduces a leakage current by raising the source potential of a memory cell to be higher than the VSS level during SRAM resume standby is proposed (Japanese Unexamined Patent Application Publication No. 2004-206745). In this technique, 0.4V is applied to the source of the memory cell. On the other hand, 1.0V is applied as a power supply potential to bit lines.
Besides, a technique that sets bit lines in floating state during resume standby in order to prevent an excessive leakage current from flowing due to a hardware defect such as fixation of a memory cell internal node to Low level is proposed (Japanese Unexamined Patent Application Publication No. 2010-198729).
In the resume standby mode of a resume standby circuit, a channel leakage is reduced by raising the source potential of a memory cell to be higher than the VSS level, thereby reducing a leakage current of the whole module. In this mode, a voltage at the VDD level or the level lower than VDD by NMOS Vth is applied to the bit lines. On the other hand, in the recent microfabrication process, a leakage current to the substrate of an access transistor through the bit lines is large due to GIDL (Gate Induced Drain Leakage), and particularly at room temperature, a leakage current cannot be sufficiently reduced in a normal resume standby circuit.